1. Field of the Invention
The present invention relates to a method of planarizing a wafer. More particularly, the present invention relates to a chemical-mechanical polishing (CMP) process for the planarization of a wafer.
2. Description of the Related Art
In semiconductor manufacturing, only a plane surface with very little height difference can avoid the dispersion of light and achieve a high degree of accuracy in a pattern transfer. Therefore, surface planarization is an important technique for dealing with high-density photolithography. At present, CMP is an important means for providing global planarization in the process of manufacturing integrated circuits.
CMP is a process that utilizes the reagent within a slurry to react chemically with the front face of a wafer and produce an easily polished layer. Together with the abrasive action provided by the abrasive particles in the slurry above a polishing pad, the protruding portion of the easily polished layer is gradually removed. By repeating the foregoing chemical reaction and mechanical polishing steps, the surface of the wafer is planarized. In general, a number of variables can affect the CMP process. This includes the pressure applied to the polishing head, the planarity of the wafer, the rotational speed of the wafer and the polishing pad, the chemical composition of the slurry and the abrasive particles, the operating temperature, the material and abrasive properties of the polishing pad and so on.
In most CMP process, the polishing has to be completed in two or more stages using a different polishing slurry in each step. For example, in the polishing of a shallow trench isolation (STI) structure, the silicate base slurry, like SS25 (available from Cabot Microelectronics) is applied in a polishing process to condition the external profile of a wafer. Then, high-selectivity slurry (HSS) such as the ceria base slurry, like Silect6000 (available from Cabot Microelectronics) is used in another polishing process so that the determination of the polishing end point is made clearer. Finally, de-ionized water is used to clear away any residual material on the wafer. In general, the slurries contain some active polishing ingredients such as abrasive particles. The abrasive particles are fabricated from aluminum oxide, silicon oxide or cerium oxide, for example.
It should be noted that the slurry SS25 has a pH value between 10 and 11 and the pH value of HSS is between 5 and 6. Therefore, if some residue from the slurry SS25 is directly transferred into the next polishing stage and mixed with the slurry HSS, a pH shock will occur and some of the cerium oxide and silicon oxide will congregate into lumps. Furthermore, the mixing of two different types of slurries will also contribute to a cross contamination of materials too. In addition, cerium oxide will carry a positive charge while the silicon oxide at a pH environment of about 5 will carry a negative charge. Thus, when the residue from the slurry SS25 contacts the slurry HSS (pH=5), they may clump together due to electrostatic attraction to form large particles.
FIG. 1 is a graph with curves showing the relationship between the particle size (the horizontal axis) and the frequency of appearance (the vertical axis). As shown in FIG. 1, curve 1 shows the frequency distribution of the size of the abrasive particles in the HSS slurry; curve 2 shows the frequency distribution of the size of the abrasive particles in the SS25 slurry; curve 3 shows the frequency distribution of the size of the particles and clumped particles inside the mixture formed by mixing the slurry SS25 and HSS in the ratio of 1:100; and, curve 4 shows the frequency distribution of the size of the particles and clumped particles inside the mixture formed by mixing the slurry SS25 and HSS in the ratio of 1:1000. As shown in region A of FIG. 1, any residual SS25 slurry remaining on the wafer surface can produce large particles when mixed with HSS slurry. These large particles may scratch against the wafer surface in a polishing process to produce serious damages in the wafer.